Advances in microelectronic (e.g., semiconductor) manufacturing technology have resulted in, among other things, significant reductions in the cost of sophisticated electronics. As a result, integrated circuits have become ubiquitous in the modern environment.
Integrated circuits are typically manufactured in batches. Individual batches typically contain multiple semiconductor wafers or other substrates, within and upon which integrated circuits are formed. Forming the integrated circuits requires a wide variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, planarizing, and other processes.
Each wafer typically includes hundreds of individual dies which are later separated or singulated and packaged for use. Before the dies are singulated, completed wafers are tested to determine which dies on the wafer are capable of operating according to predetermined specifications. In this manner, integrated circuits that cannot perform as desired are not packaged or otherwise incorporated into finished products.
It is typical to manufacture integrated circuits on roughly circular semiconductor substrates or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on or close to the uppermost layers of the integrated circuits are available to act as terminals for connections to various electronic elements disposed in, or on, the lower layers of the integrated circuits. During testing, these conductive regions are commonly contacted with a probe card.
Historically, unsingulated integrated circuits on a wafer were tested one at a time. In order to reduce costs and improve return on investment, the amount of time that each wafer spends in the testing process should be reduced. Various methods and apparatuses have been sought by manufacturers for testing two or more integrated circuits at the same time. In this way, wafer throughput can be increased. A typical requirement for testing more than one integrated circuit at a time is to increase the number of tester channels on the tester. In such a parallel testing arrangement, when a first one of the two or more integrated circuits is determined to fail the test program, the one or more remaining integrated circuits in that group must continue with, and complete, the test sequence before another group of integrated circuits on the wafer can begin the process of testing. This means that the tester channels dedicated to the integrated circuit that failed are not usefully occupied until the test system is ready to test the next group of integrated circuits on the wafer. Accordingly, there remains a need for more efficient wafer testing, particular in the light of the increased concentration and complexity of integrated circuits on wafers.